Secured chips are mostly used in manufacturing of smart cards, security modules, identification devices and other integrated circuits used in applications requiring a high security level.
Document WO2010/130709A1 discloses a method for authenticating access to a secured chip by a test device. Once the test device is authenticated with the chip, i.e. successful verifications have been made by control data exchanges between the test device and the chip, the different operating tests or simulations are carried out on hardware and software functions and/or programs implemented in the chip. The test device can also comprise functionalities of configuration or customization of the chip by enabling, disabling or programming features according to the applications requirements foreseen for the chip. According to a preferred implementation, one advantage of this method is minimizing the data transfer between the test device and the secured chip. In response of a challenge produced by the chip, the test device sends a cryptogram which will be analyzed and verified by the chip before authorizing the test device to perform tests on said chip.
The document EP1441313 handles on an asymmetrical cryptographic method of protecting a hard-wired electronic logic chip against fraud in transactions between the electronic chip and an application including calculating an authentication value from input parameters in the electronic chip. The method comprises the steps of: producing by the chip a random number specific to the transaction; sending to the application a first parameter calculated by the application prior to the transaction, linked to the random number by a mathematical relationship, and stored in a data memory of the chip; calculating by the chip a second parameter constituting an authentication value by means of a serial function whose input parameters are at least the random number specific to the transaction and a private key belonging to an asymmetrical key pair; sending the authentication value to the application, and verifying said authentication value by means of a verification function whose input parameters consist exclusively of public parameters including at least the public key.
The document EP1983466 describes method and apparatus of secure authentication for system on a chip (SoC). The SoC may enable authentication of an external entity attempting to gain access to a function or system. The SoC and an authorized external entity may each have knowledge of hidden data prior to an authentication attempt and may communicate data during the authentication process as well. Using like data, the SoC and external entity may be able to generate the same password and achieve system access. Passwords may be unique in two ways, for example: per operation and per SoC device. A random number generator on board the SoC may enable the passwords to vary for each iteration of the authentication process. Each instance of a SoC has its own secret word allowing passwords to be unique for each device.
After manufacturing, smart card integrated circuits or chips need to be personalized to embed unique secrets and to load application code in a very secure way to prevent cloning or reprogramming smart cards made with these chips. Classical solutions are based on a dedicated computer station that allows instructed personnel to program the cards at personalization facility (in-house or external). This approach has many weak aspects and to overcome these issues following requirements are considered:    a) Render personalization possible only at wafer level and extremely difficult to re-activate with physical means once the wafer is cut and the chip are packaged.    b) The personalization activation should not rely only on a single secret or on software package that can be owned (and leaked) by personnel at personalization facility.    c) Render replaying personalization sequences impossible in order to clone chips intended to be implemented in smart cards.    d) Prevent complete reverse engineering of the smart card chip allowing an attacker reproducing the chip personalization.